1. Field of the Invention
The present invention relates to three-dimensional (3-D) integrated circuits, and in particular to increasing the processing window for interlayer conductors contacting landing regions of active layers.
2. Description of Related Art
3-D integrated circuits include multiple active layers in which conductive or semiconductive elements are disposed. 3-D memory integrated circuits include stacks of two-dimensional arrays of memory cells. Active layers in the stacks can include bit lines or word lines for example, which must be connected to peripheral circuits like decoders, sense amplifiers and the like. In some arrangements, the connections are made using interlayer conductors that extend from each active layer to a routing layer, such as a patterned metal layer that overlies the stacks of two-dimensional arrays. The patterned metal layer can be used to route signals and bias voltages between the arrays and the appropriate peripheral circuits. Similar signal routing structures can be used on other types of 3-D integrated circuits.
3-D integrated circuits also include other types of structures including 3-D vertical gate structures and 3-D vertical channel structures. Both of these stacks have alternating active layers and insulating layers with interlayer conductors extending to landing regions, also referred to as landing pads, on the various active layers.
The interlayer conductors have lengths that vary in dependence on the active layer to which contact is made. As the number of active layers increases, some of the processes involved in formation of interlayer conductors can become more difficult. One reason for the difficulty is that as the length of the interlayer conductor increases, the interlayer conductor tapers to a smaller diametrical dimension so that the landing window between the interlayer conductor and the landing region on the active layer decrease.